Computer systems, software applications, and the devices and processes built around them are continually growing in power and complexity. Society's reliance on such systems is likewise increasing, making it critical that the systems obey the properties that their designers intended. Typically, the more powerful and complex the system, the greater its utility and usefulness. However, as these computer and software implemented systems and processes become more powerful, detecting and correcting flaws within the systems becomes increasingly difficult.
The development of ASICs (application specific integrated circuits) and other complex integrated circuits with the aid of CAD tools is referred to as electronic design automation, or EDA. Design, checking, and testing of large-scale integrated circuits are so complex that the use of programmed computer systems are required for realization of normal circuits. This is partly because the integrated devices are inherently complex and partly because the circuit design needs to be decomposed into simpler functions which are recognized by the CAD tool. It is also partly because considerable computation is required in order to achieve an efficient layout of the resultant network. The result of the computerized design process is a detailed specification defining a complex integrated circuit in terms of a particular technology. This specification can be regarded as a template for the fabrication of the physical embodiment of the integrated circuit using transistors, routing resources, etc.
Integrated circuit designs can be represented in different levels of abstraction, such as the register transfer level (RTL) and the logical level, using a hardware description language (HDL), also called high level design language. Two exemplary forms of HDL are Verilog and VHDL. The integrated circuit can be represented by different layers of abstractions (e.g., behavioral levels, structural levels and gate levels). An RTL level is an intermediary level of abstraction between the behavioral and structural levels. HDL descriptions can represent designs of all these levels.
The behavior levels and RTL levels consist generally of descriptions of the circuit expressed with program-like constructs, such as variables, operators conditional loops, procedures, and functions. At the logic level, the descriptions of the circuit are expressed with Boolean equations. The HDL can be used along with a set of circuit constraints as an input to a computer-implemented compiler (also called a "silicon compiler"). The computer-implemented compiler program processes this description of the integrated circuit and generates therefrom a detailed list of logic components and the interconnections between these components. This list is called a "netlist." The components of a netlist can include primitive cells such as full-adders, NAND gates, NOR gates, XOR gates, latches, and D-flip flops, etc., and their interconnections can be used to form a custom design.
In processing the HDL input, the compiler first generates a netlist of generic primitive cells that are technology independent. The compiler then applies a particular cell library to this generic netlist (this process is called mapping) in order to generate a technology-dependent mapped netlist. The mapping process converts the logical representation which is independent of technology into a form which is technology dependent. The mapped netlist has recourse to standard circuits, or cells, which are available within a cell library forming a part of the data available to the computer system.
Compiler programs and mapping programs are well known in the art, and several of these systems are described in U.S. Pat. No. 5,406,497, by Altheimer et al.
As ASICs and other complex integrated circuits have become more complex and more dense, they have become progressively harder to test in order to ensure correct and complete functionality. For example, with current technology, as the number of gates and transistors increase, the time which an ASIC emerging from a fabrication process line spends in testing increases as well. This increase incurs an additional cost on ASIC manufacturing. The testing cost can be very significant for the latest and largest memories. In addition, as more complex systems-on-a-chip devices proliferate, which, for example, integrate complex logic units (integer units, floating point units, memory, etc.) into a single chip, and as newly-designed processors begin to take advantage of the ability to integrate large quantities of memory on-chip, it has become necessary to increase the comprehensiveness, efficiency, and accuracy of the design checking and testing schemes utilized to ensure proper operation of these devices (e.g., ASICs, complex integrated circuits, field programmable gate arrays, etc.).
Thus, an increasingly important part of the logic synthesis and testing process involves designing ASICs and other complex integrated circuits for inherent testability. Programs that aid in the testability process of logic synthesis are called design for test (DFT) processes. As part of DFT, it is well known to take the mapped netlist generated from a compiler and add and/or replace certain memory cells and associated circuitry with special memory cells that are designed to allow the application of test vectors to certain logic portions of the integrated circuit. The act of applying test vectors is called stimulation of the design, and the special memory cells and associated circuitry are referred to as DFT implementations. Issues concerning controllability deal with facilitating the application of the test vectors to the circuitry to be tested. The same memory cells can be used to capture the output of the circuitry for observation and compare this output to the expected output in an effort to determine if circuit (e.g., manufacturing) defects are present.
The portions of an integrated circuit that are designed to perform its intended or expected operational function are called its "mission mode" circuitry, while the portions added to the integrated circuit to facilitate testability are called "test mode" circuitry or DFT implementations. The resultant circuit, therefore, has two functional modes, mission and test.
Prior art FIG. 1A shows an exemplary flow chart diagram of a typical prior art logic synthesis process, including a DFT process. The processes 200 described with respect to this flow chart is implemented within a computer system in a CAD environment. High level design language (HDL) descriptions of the integrated circuit enter at block 201. Accompanying the HDL 201 is a set of performance constraints applicable to the design which typically include timing, area, power consumption, and other performance related limitations that the compiler (e.g., in step 202) will attempt to satisfy when synthesizing the integrated circuit design. These constraints can also include non-performance related constraints such as structural and routing constraints. In step 202, the HDL descriptions of the integrated circuit are compiled. The compiler (also called an HDL compiler, RTL synthesizer, or architectural optimizer) inputs the HDL 201 description and generates therefrom a technology independent or "generic" netlist. The generic netlist is then compiled using logic optimization procedures and a mapping procedures which interface with a technology dependent cell library 204 (e.g., from LSI, VLSI, TI or Xilinx technologies, etc.). The cell library 204 contains specific information regarding the cells of the specific technology selected such as the cell logic, number of gates, area consumption, power consumption, pin descriptions, etc., for each cell in the library 204. The compiling procedure of block 202 ultimately generates a gate level mapped netlist 203 that is technology dependent having cells specifically selected in accordance with the particular manufacturing technology being used to fabricate the device.
At block 205 of FIG. 1A, DFT process performs a particular test insertion process (here a scan) to implement testability cells or "test mode" cells into the overall integrated circuit design. In this process 205, memory cells of the mapped netlist 203 are replaced with memory cells that are specially designed to apply and observe test vectors or patterns to and from portions of the integrated circuit. In one particular DFT process, these memory cells specially designed for test are called scannable memory cells. The test vector patterns can be derived from combinational or sequential automatic test pattern generation (ATPG) processes depending on whether or not a full or partial scan is performed by the scan insertion process 205. Process 205 also performs linking groups of scannable memory cells into scan chains so that the test vectors can be cycled into and out of the integrated circuit design. The output of the scan insertion process 205 is a scannable, or scanned, netlist 206.
The scanned netlist 206 is then subjected to automatic test pattern generation tools in block 207. The out of a test pattern generation tools apply a specific procedure referred to as "design rule checking", or DRC, to determine whether the tools properly understand and can properly interpret the parameters, interconnections, etc. of the scanned netlist 206. DRC functions by verifying whether the specific format or protocols of the scanned netlist 206 match the constraints and/or formats used by the ATPG (automatic test pattern generation) tool. If the scanned netlist 206 passes combinational ATPG DRC, the scanned netlist 206 is passed to step 208 for combinational ATPG processing. Automatic test pattern generation processing in step 208 is performed using a set of specific test constraints 213 which were created by a user in step 212, or otherwise obtained from design processes. As depicted in diagram 200, the ATPG processing of block 208 is performed using combinational techniques. The result of this processing is a test program 209 adapted for application to automatic test equipment. In block 210, test program 209 is verified to determine whether it meets requirements for the device. If the test program meets requirements, the test program is used with automatic test equipment in block 211 to apply test vectors to the scannable cells inserted in step 205.
However, the problem with the prior art process of diagram 200 is the fact that scanned netlist 206 often will not pass ATPG DRC in step 207. This leads to number of serious consequences. These consequences often add complexity, expense, and time consumption to the design process. As shown in FIG. 1A, if the scanned netlist 206 does not pass ATPG DRC in step 207, a number alternatives are pursued.
A first alternative 220 is depicted in FIG. 1B. In this alternative, combinational ATPG processing is abandoned in favor of sequential ATPG processing. Sequential processing has the advantage of being less restrictive with regard to the parameters, formats, etc. of scanned netlist 206. However, sequential processing has a very serious disadvantage in that it is far more processor intensive and time-consuming than combinational processing.
A second alternative 230 is depicted in FIG. 1C. In this alternative, the original test constraints 212 are modified in block 231, resulting in new test constraints 232. The new test constraints 232 will hopefully allow scanned netlist 206 to pass a re-executed combinational ATPG DRC in block 233. In block 234, if design rule checking is passed, the process returns (back to combinational ATPG processing in step 208). If not, the test constraints may be modified again.
A third alternative 240 is depicted in FIG. 1D. In this alternative, as opposed to modifying the original test constraints 212, the original scan insertion 205 is modified in block 241, resulting in a new scan to netlist 242. This new scanned netlist 242 is then processed for ATPG DRC. If DRC is passed, in block 243, the process returns (back to combinational ATPG processing in block 208). If not, the scan insertion may be modified again.
FIG. 1E shows a process 250 which are used when the test program 209 does not meet the test requirements in step 210. In steps 251, 252, and 253, the test program is manually modified, by a design engineer, for example, to obtain a new test program which is subsequently check to determine whether it meets test requirements. The designer is free to manually modify the test program in any of a number of ways in hopes of making the program meet test requirements. If the test program meets requirements, the process returns (back to block 211 of FIG. 1A).
Thus, the prior art process 200 of FIG. 1A has several disadvantages. It is disadvantageous to execute sequential ATPG processing as shown in FIG. 1B, if it can be avoided at all. Thus, it is very disadvantageous to have scanned netlist 206 not pass ATPG DRC in block 207. It is disadvantageous to have to modify test constraints multiple times in order to coax the scanned netlist 206 into passing ATPG DRC, as depicted in FIG. 1C. Similarly, it is disadvantageous to have to modify the scan insertion multiple times in hopes of coaxing the scanned netlist 206 into passing ATPG DRC, as depicted in FIG. 1D.
Each of the above modifications require new, time-consuming, compiles. Although one or more of these compiles can be an incremental compile step in that much of the gate level connections are not removed, mapping optimization portions of this compile process still operate in an iterative fashion over the entire design. The addition of this additional compile processes, using conventional technology, delays the overall integrated circuit synthesis process by as much as one to two weeks. Even after this long delay, there are no guarantees that the additional compiles will generate a scannable netlist satisfying ATPG DRC in step 207.
With respect to the alternative shown in FIG. 1E, the task of manually modifying the test program in step 251 is one of the most time-consuming and error prone of the above processes. This involves and engineer manually sifting through data sheets to modify any number of test vectors included in the test program. It is highly desirable, especially in a computer-aided design environment, to avoid manually returning to the HDL design or the test program for manual adjustments and tinkering. The cumulative effect of the above limitations results in the fact that the number/types of scanned netlists 206 which can be used in the design synthesis process is greatly limited.
Thus, what is required is a system which provides an order of magnitude improvement in run-time performance for ATPG and similar analysis-related programs. What is required is a system which allows ATPG analysis and processing of scannable netlists which may not adhere to conventional DFT design rules and which thereby allows the analysis and processing of a broader variety of circuit types. What is required is a system which provides a time-efficient design synthesis system operable within a computer-implemented CAD system that includes effective DFT processes. What is further required is a system which effectively broadens the constraints with which the scannable netlist is subjected, thereby reducing the complexity and the amount of time required in recompiling the HDL design. Additionally, what is further required is a system which provides for increased testing coverage of a resulting design, thereby providing more efficient testing completed devices.